The invention applies generally to the field of obtaining and maintaining synchronization to a digital signal. Especially the invention applies to the task of obtaining and maintaining frame synchronization when the received digital signal comprises a constant frame alignment signal which is a bit sequence distributed over a relatively long frame length.
Synchronization to digital signals in general has been treated for example in the patent publication U.S. Pat. No. 4,434,498, where a digital signal is formed from successive words that represent samples of sound information comprising silent periods. The receiving device stores the words into a memory as they arrive. The stored words are read at a local clock frequency. The receiving device determines the filling rate of the memory and compares this rate with a given allowed range. If the filling rate is not within the range, the receiving device modifies the contents of the memory when the next silent interval appears.
The patent U.S. Pat. No. 4,573,172 presents a programmable circuit for the serial-parallel transformation of a digital signal. The solution comprises also a circuit for detecting the appearance of certain synchronizing words in the digital signal. A parallel clock signal is generated by a programmable divider from the clock frequency of the serial signal. The circuit monitors the coincidences between the parallel clock signal and pulses characteristic of the times when synchronizing words are detected. A logic circuit transfers an indication to a sync control input of a programmable divider when a predetermined programmable number of successive non coincidences or coincidences has been detected.
The patent U.S. Pat. No. 5,331,668 discloses a communication control device in which a clock frequency for processing communication data is the same as or lower than the transfer speed of the communication data. The author promises that a complicated construction of the input-output portion to the network is not required, so it should be possible to realize low power consumption and easy design and manufacture of the device.
The CCITT (Comitxc3xa9 Consultatif International Txc3xa9lxc3xa9phonique et Txc3xa9lxc3xa9graphique) Recommendation number G.704 and the European Telecommunications Standard number ETS 300 800 determine a so-called T1 extended superframe or ESF structure, which consists of 4632 bit positions. A majority of these bit positions are used for payload data, while certain bit positions belong to a so-called overhead. Six specifically determined overhead bits constitute the Frame Alignment Signal or FAS for the extended superframe. These FAS bits are spaced 772 bit positions from each other in the extended superframe and they always have the same values, constituting the pattern xe2x80x9c001011xe2x80x9d when taken together in the same order in which they appear in the extended superframe. A receiver that is receiving T1 ESFs must find the repeatedly occurring FAS pattern in the received bit stream in order to establish the required knowledge about the start of each ESF and the location of more detailed data structures within the ESF. FIG. 1 illustrates some known aspects of the T1 frame and superframe structure.
Some applications require very fast synchronization to the extended superframe structure, which has prompted prior art designers to present some relatively complicated and/or processing-intensive solutions that are based either on complicated hardware logic or on pattern search algorithms. The U.S. Pat. No. 5,490,147 presents a frame alignment circuit where a shift register is used for accumulating serial data. A latch circuit converts the accumulated data into parallel data, and a programmable counter divides the associated serial clock signal into a divided, parallel clock signal. The frame alignment circuit further includes a pattern detector which should detect a frame alignment pattern of the parallel data. A separate determining circuit determines a deviation of alignment based on a reference frame alignment signal and the detected frame alignment pattern. Additionally there is a shift controlling circuit for controlling the dividing ratio of the programmable counter based on a deviation of alignment signal output by the frame alignment circuit.
The patent U.S. Pat. No. 5,621,773 is directed especially for providing and maintaining synchronization to T1 extended superframes. The disclosed device includes a memory for storing a complete extended superframe of received data. A pattern detector detects patterns in the memory that match the predetermined FAS signal. A given memory address corresponds to a particular bit position within the received data. When a pattern is detected, the corresponding address is stored into a register, and an associated counter is set to one. Subsequent pattern matches and violations at that address cause the counter to increment and decrement, respectively. Decrementing to zero makes the register available for storing a new address. In-sync is declared when a counter exceeds a certain threshold. Correspondingly out-of-sync is declared when that counter falls to another threshold or below. The synchronizer continues to search for alternative candidates even after in-sync has been declared.
The problems o the prior art solutions are associated with their excessive requirements of either memory size or processing capacity or both. Especially for fast prototyping purposes the designers often use FPGAs or Field Programmable Gate Arrays, where the implementation of large memories becomes problematic.
It is therefore the object of the present invention to provide a method and an arrangement for synchronizing to a digital signal and maintaining synchronization with low requirements of memory size and processing capacity. It is an additional object of the invention that it is readily applicable to prototyping with Field Programmable Gate Arrays.
The objects of the invention are achieved by summing several signal frames, or passages taken from a constant position within several signal frames, and looking for peaks that reveal a constant bit value at a certain bit position within the summed entities.
The method according to the invention is characterized in that it comprises the steps of
receiving a number of frames
selecting a passage from the same location within each received frame
observing a regularly occurring bit value at a constant bit position within the selected passages
as a response to an observed regularly occurring bit value, using the corresponding position in the received digital signal as a starting point and locating the rest of the distributed frame synchronization pattern within the received digital signal.
The invention also applies to a receiving device which is characterized in that it comprises
memory means for storing a combination of passages taken from a constant location within a number of received frames
observing means for observing a regularly occurring bit value at a constant bit position within the stored combination
control means for using the position in the received digital signal corresponding to the location of an observed regularly occurring bit value as a starting point and locating the rest of the distributed frame synchronization pattern within the received digital signal.
The research which led to the present invention revealed that the requirements of memory space and processing capacity can be considerably loosened if we allow the synchronization to take a somewhat longer time. According to the invention the receiving device receives a number of consecutive frames (which may be for example T1 extended superframes) and selects either certain complete frames or certain passage from a constant location within each frame of a group of accumulated frames. The selected entities are summed bitwise to each other. If there is at a certain bit position an essentially constant bit value in each summed entity, a peak value starts accumulating at the corresponding bit position in the summing result as the summing proceeds. If only a passage is selected from a constant location within each frame of a group of accumulated frames and no peaks seem to be appearing, it is possible to change the location from which the passage is taken within the frames.
To reliably detect a frame alignment signal the receiving device should find a correct peak value at each bit position which corresponds to a known location of a frame alignment bit. The (pseudo-)random nature of the rest of the bits in the frames tends to even out the summing result at all other bit positions. However, it is possible that peaks accumulate also at some other bit positions due to other regularly occurring bit patterns or even as one potential result of randomness. Therefore it is advantageous for the receiving device to check the validity of obtained synchronization by calculating a checksum that is a part of the frame structure.
After synchronization has been achieved, its validity is monitored by checking the values of the frame alignment bits most advantageously in each received frame or alternatively in a sample of received frames. Additionally or alternatively the validity of checksums may be monitored in received frames. Here we use the concept xe2x80x9cframexe2x80x9d generally to refer to all such repeatedly occurring structures in the received bit stream that are applicable to the detection of alignment bits and calculation of checksums. If the monitoring shows that synchronization has been lost, the procedure for sync acquisition is started again.